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NCP1631
(V in,avg ) boH * (V in,avg ) boL 1 * 10
? The 7 ? m A current source is enabled that lowers
the pin7 voltage for hysteresis purpose.
A short delay (T delay ) is added to get sure that these three
actions are properly done before the PFC driver is disabled
and the “V control ” and “pfcOK” pins are grounded.
At startup (and in UVLO situations that is when the Vcc
voltage is not sufficient for operation), a pnp transistor
ensures that the BO pin voltage remains below the 1 V
threshold until V CC reaches V CC(on) . This is to guarantee
that the circuit starts operation in the right state, that is,
“BONOK” high. When V CC exceeds V CC(on) , the pnp
transistor turns off and the circuit enables the 7 ? m A current
source (I BO ).
Also, (I BO ) is enabled whenever the part is in off ? mode,
but at startup, I BO is disabled until V CC reaches V CC(on) .
Brown ? out Resistors Calculation
The BO resistors can be calculated with the following
equations (for more details, refer to the application note
AND8407)
f line
3 f line
temperature exceeds 140 ° C typically. The output stage is
then enabled once the temperature drops below about 80 ° C
(60 ° C hysteresis).
The temperature shutdown keeps active as long as the
circuit is not reset, that is, as long as V CC keeps higher than
V CC RESET. The reset action forces the TSD threshold to
be the upper one (140 ° C). This ensures that any cold
start ? up will be done with the right TSD level.
Under ? Voltage Lockout Section
The NCP1631 incorporates an Under ? Voltage Lockout
block to prevent the circuit from operating when the power
supply is not high enough to ensure a proper operation. An
UVLO comparator monitors the pin 12 voltage (V CC ) to
allow the NCP1631 operation when V CC exceeds 12 V
typically. The comparator incorporates some hysteresis
(2.0 V typically) to prevent erratic operation as the V CC
crosses the threshold. When V CC goes below the UVLO
comparator lower threshold, the circuit turns off.
The circuit off state consumption is very low: < 50 m A.
This low consumption enables to use resistors to charge
the V CC capacitor during the start ? up without the penalty
of a too high dissipation.
R bo1 +
I HYST
(eq. 23)
Output Drive Section
The circuit embeds two drivers to control the two
1 * BO
R bo2 +
(V in,avg ) boL
V BO(th)
R bo1
f
3 f line
* 1
(eq. 24)
interleaved branches. Each output stage contains a totem
pole optimized to minimize the cross conduction current
during high frequency operation. The gate drive is kept in
a sinking mode whenever the Under ? Voltage Lockout
(UVLO) is active or more generally whenever the circuit
Feed ? forward
As shown by Figure 19, The BO circuit also generates an
internal current proportional to the input voltage average
value (I Rt ). The pin7 voltage is buffered and made available
on pin 3. Placing a resistor between pin 3 and ground,
enables to adjust a current proportional to the average input
voltage. This current (I Rt ) is internally copied and squared
to form the charge current for the timing capacitor of each
phase. Since this current is proportional to the square of the
line magnitude, the conduction time is made inversely
proportional to the line magnitude. This feed ? forward
feature makes the transfer function and the power delivery
independent of the ac line level. Only the regulation output
(V REGUL ) controls the power amount. If the I Rt current is
too low ( below 7 m A), the controller goes in OFF mode to
avoid damaging the MOSFETs with too long conduction
time.
Thermal Shutdown (TSD)
An internal thermal circuitry disables the circuit gate
drive and then keeps the power switch off when the junction
is off. Its high current capability ( ? 500 mA/+800 mA)
allows it to effectively drive high gate charge power
MOSFET.
Reference Section
The circuit features an accurate internal reference
voltage (V REF ). V REF is optimized to be ± 2.4% accurate
over the temperature range (the typical value is 2.5 V).
V REF is the voltage reference used for the regulation and
the over ? voltage protection. The circuit also incorporates
a precise current reference (I REF ) that allows the
Over ? Current Limitation to feature a ± 6% accuracy over
the temperature range.
Fault Management and OFF Mode
The circuit detects a fault if the R t pin is open (Figure 20).
Practically, if the pin sources less than 7 m A, the “I Rt_Low ”
signal sets a latch that turns off the circuit if its output
(R t(open) ) is high. A 30 ? m s blanking time avoids parasitic
fault detections. The latch is reset when the circuit is in
UVLO state (too low V CC levels for proper operation).
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20
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